1. Field of the Invention
The present invention relates to the processing of substrates such as semiconductor wafers using electron beam lithography. More specifically, the present invention relates to methods for forming a mask pattern on a resist using electron beam lithography such that write time is reduced.
2. State of the Art
Semiconductor devices including integrated circuitry, such as memory dice, are mass produced by fabricating hundreds or even thousands of circuit patterns on a single semiconductor wafer or other bulk semiconductor substrate using lithographic processing in combination with various other processes. In order to increase the number of memory cells on semiconductor memory devices for a given surface area, it is important to accurately control the resolution of the images produced during lithography. These images are used to define structural features on a semiconductor substrate in fabricating the integrated circuitry of such semiconductor memory devices.
Photolithography is a process in which a pattern is delineated in a layer of material, such as a photoresist, sensitive to photons. In photolithography, an object containing a pattern (e.g., reticle or mask) is exposed to incident light. The image from the reticle or mask is projected onto a photoresist that covers a semiconductor wafer or other substrate. The photolithographic process typically involves exposing and developing the photoresist multiple times. At a given step, the photoresist is selectively exposed to photons and then developed to remove one of either the exposed or unexposed portions of photoresist, depending on whether a positive or negative photoresist is employed. Complex patterns typically require multiple exposure and development steps.
Currently, conventional photolithography using light is only capable of producing structural features of about 100 nm in minimum dimension. This inadequacy limits the ability of a manufacturer to produce extremely small structural features for integrated circuits through conventional photolithography processes. A capability to further reduce the dimensions of structural feature size is particularly important to the fabrication of semiconductor memory devices to enable an increase in the number of memory cells on such semiconductor memory devices of a given size.
In order to produce structural features smaller than the capability of photolithography, electron beam lithography (EBL) has been developed. EBL produces a desired pattern on a resist by irradiating a resist sensitive to electrons with an appropriate amount of electrons on specific portions of the resist. In a typical variable-shaped vector scan EBL process, the electron beam emitter is positioned over only specific sites of the resist and the resist is exposed to a shaped beam of electrons, called a shot. Positioning is accomplished by a combination of movement of the substrate stage in the X-Y direction in the plane of the substrate, and/or movement of the electron beam. Thus, the pattern data used by the EBL system must be provided with information that includes both the dose of electrons and the position of each site on the resist to be exposed for each shot.
The typical variable-shaped vector scan EBL process decomposes a pattern into rectangular-shaped or 45° angle triangular-shaped “primitives.” The rectangles are aligned along the X-Y axes in the plane of the substrate defining the vector scan. The 45° angle triangular-shaped primitives are only capable of exposing features positioned at a 45° angle without using an excessive number of shots. The electron beam from the EBL system is capable of exposing a primitive in a single shot. As shown in FIGS. 1A and 1B, for a typical vector scan, a substantial portion of the pattern is made up of triangles approximated by various sizes of rectangles, while only a small portion of the pattern is made up of true rectangles. Because the write time is proportional to the number of shots, this use of small rectangles to approximate triangles requires a great number of shots and takes up to 90% of the exposure time. Furthermore, it results in loss of fidelity of the mask pattern produced on the resist as shown by the stepped edges in the triangular regions in FIGS. 1A and 1B.
Due to the long exposure times that are inherent in using small rectangles to approximate triangles, cell projected EBL may be used. In cell projected EBL, a variable-shaped electron beam, typically having the shape of the desired cell pattern or the shapes at various angles, is used to produce these non-rectangular shapes. The variable shape is produced by passing the electron beam through an aperture having the desired shape. When a variable-shaped beam is used, the pattern data used by the EBL system includes the dose of electrons, location, size, and shape for each shot. Although cell projected EBL reduces the write time required to expose a pattern, the total throughput is still undesirably too long. Also, it is difficult to prepare enough non-rectangular-shaped apertures to accommodate the multitude of patterns an integrated circuit designer may desire to use. Furthermore, using multiple apertures of varying shapes causes difficulties in the beam alignment and calibration of the EBL system. Examples of apparatus and methods for variable-shaped EBL are shown in U.S. Pat. No. 6,573,516 to Kawakami; U.S. Pat. No. 6,455,863 to Babin, et al.; U.S. Pat. No. 6,259,106 to Boegli, et al.; U.S. Pat. No. 5,760,410 to Matsuki, et al.; and U.S. Pat. No. 4,532,598 to Shibayama, et al.; each of the disclosures of which are herein incorporated by reference for all that they disclose.
The problem with write time is exacerbated by the new generation of integrated circuit designs that use “angled line” features, as shown by FIG. 2. In FIG. 2, the exposed regions 202 (dark) are the resist regions that have been exposed to the shots of an electron beam from an EBL system. The exposed regions 202 are made up of individual shots of primitive rectangles 206, which form the angled features on the resist. The exposed regions 202, otherwise known as the angled line features, are formed by using multiple stepped, or partially offset, rectangular shots. The exposed regions 202 exhibit a loss of fidelity as shown by the stepped edges 208 that form the angled features. The loss of fidelity in the mask pattern is an artifact of the processing because the exposed region 202 would, ideally, exhibit smooth linear edges as represented by the design data for the integrated circuit layout. The lighter regions are the unexposed regions of resist 204. In order to increase the number of memory cells on semiconductor memory devices for a given surface area, integrated circuit designers lay out the features at a certain angle to maximize the use of the substrate surface area. However, this angled line layout makes it more expensive to generate the pattern on the resist because of the numerous non-rectangular shapes that must be used to form the pattern, resulting in undesirably long write times and the great number of rectangular shots from the electron beam required to form the angled features.
Accordingly, a need exists to develop a method for generating angled features on resist using electron beam lithography wherein the write time is reduced compared to conventional EBL methods. Another need exists for a method to modify conventional EBL systems such that the method may be implemented by modification of a semiconductor manufacturer's existing equipment.